The present invention relates to the mounting of integrated circuits on circuit boards and, more specifically, to the 3-D stacking of thinned die before mounting.
The development of thinned die on thin film flexible multilayer circuit boards has progressed to the demonstration state (see, for example, H. K. Charles, Jr., A. S. Francomacaro, S. J. Lehtonen, A. C. Keeney, G. V. Clatterbaugh, and C. V. Banda “Development of Ultra-thin Microelectronic Chip Assemblies”, proc. 42nd International Symposium on Microelectronics, San Jose, Calif. Nov. 1-5, 2009; and U.S. patent application Ser. No. 11/756,816, filed Jun. 1, 2007, published Jan. 10, 2008, publication no. 2008/0009095, the contents of both being incorporated herein by reference in their entireties).
The microelectronic assemblies, as described in the above references, are for planer applications in which the heat removal from the die is envisioned to be accomplished through the substrate. While these assemblies are extremely flexible and have a myriad of applications ranging from curved surface appliqués to embedded clothing devices, they are planar in nature.
Recent trends in modern electronic packaging have stressed the need to preserve surface real estate by stacking components one on top of the other. Stacking presents the circuit developer with two major challenges: 1) connecting the various die on the vertical stack and 2) removing the heat, since the power density on a given volume increases rapidly upon stacking.
What is needed then are apparatus and methods for stacking thinned die that address both of the above concerns while still keeping stacked component size small.